Flash memory is a type of electronically Erasable Programmable Read-Only Memory (EEPROM). An EEPROM is a memory that can be erased by applying a signal across the memory cell array. Flash memory, unlike EEPROM memory, can be erased in discrete blocks. Flash memory is useful as non-volatile memory for computer systems, digital cameras, portable storage, etc. A flash memory array typically includes numerous individual cells that comprise transistors including two gates: a floating gate and a control gate. The control gate of an individual cell can be activated by propagating a signal along the appropriate bit line and word line, which reprograms the cell.
FIGS. 1A-1C illustrate a virtual ground (VG) erasable tunnel oxide (ETOX) flash memory cell array 100. FIG. 1A illustrates an overhead view of the flash memory cell array 100, FIG. 1B illustrates a view along a word line (i.e., the line 101a) of the flash memory cell array 100, and FIG. 1C illustrates a view across a two word lines of the flash memory cell array (i.e., the line 101b).
A VG ETOX flash memory cell array has the advantage of requiring a single contact for several cells (as many as 32 or more), rather than the one contact for every two cells required by a standard ETOX flash cell. The VG ETOX flash memory cell array 100 (see FIG. 1A) includes several gate stacks 102 (see FIG. 1C) that each defines an individual memory cell. The gate stacks 102 include two layers of polysilicon 104 and 106 (see FIGS. 1B and 1C) that define a floating gate and a control gate, respectively. In a VG ETOX flash memory cell array, adjacent gate stacks 102 (for example, the gate stacks 102a and 102b) are very close together, since there is no contact between the stacks 102. The distance between the gate stacks 102 may be as small as the lithography tools allow (for example, 45 nanometers). The close proximity of two gate stacks 102a and 102b can lead to cross-coupling between the gate stacks, and the inadvertent disturbance of adjacent memory cells.
Each gate stack 102 also has a layer of conductive silicide or metal 108 on top of the stack to create a low resistance control gate for the stack. A dielectric film 110 (see FIG. 1C) is typically deposited between two gate stacks 102a and 102b to prevent conduction of the region between the gate stacks 102a and 102b, thereby preventing shorts between two gate stacks 102a and 102b. The film 110 fills the cavity between the gate stacks 102a and 102b. 
The gate stacks are formed using a multi-step process of growing, depositing, etching, etc., various semiconductor, dielectric, and conductive materials on a substrate 112 (see FIGS. 1B and 1C). The substrate 112 is a silicon substrate including several doped regions 114 (see FIG. 1B) that form source and drain regions. The several layers of the flash memory cell array 100 include a tunnel oxide layer 116, a self-aligned oxide 118 deposited over the doped regions 114, the floating gate comprising the first layer of polysilicon 104, an oxide-nitride-oxide (ONO) layer 120, the control gate comprising the second layer of polysilicon 106, and the silicide layer 108 (see FIGS. 1B and 1C). The flash memory cell array 100 further includes several source/drain (S/D) diffusions 122 and word lines 124 (see FIG. 1A).
As the size of flash memory cells is further reduced, the gap between the gate stacks 102 becomes smaller and smaller. A parasitic coupling on one floating gate may reprogram an adjacent floating gate, potentially resulting in data corruption or loss.